发明名称 Parallel byte processing engines shared among multiple data channels
摘要 A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol. When processing ATM cell bytes, the method and apparatus further includes multiple parallel quad-byte processing engines for calculating cell delineation values, and multiple comparators for comparing the calculated cell delineation values with respective bytes from the second set of bytes to identify ATM start bytes contained in the first set of bytes.
申请公布号 US2002141450(A1) 申请公布日期 2002.10.03
申请号 US20010828573 申请日期 2001.04.02
申请人 DUVVURU RAMESH 发明人 DUVVURU RAMESH
分类号 H04L12/56;H04L29/06;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04L12/56
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