| 摘要 |
The invention relates to methods and apparatus that reset integration capacitors at high frequencies to prepare the integration capacitors to store an integration result of a transition between adjacent data bits in a serial bitstream. In one embodiment of an integrating phase detector having a reset circuit, the reset circuit resets the integration capacitors, the integrating phase detector then integrates a transition of a serial bitstream with the integration capacitors, and the integrating phase detector combines the integration results of multiple integrations with a multiplier circuit. The reset circuit couples to clock phases of a control clock, such as to a voltage controlled oscillator configured to synchronize to the serial bitstream, and is configured to time the reset of the integration capacitors so as not to occur when the integrating phase detector is integrating a transition in the integration capacitors or when integration results are dumped by the multiplier circuit.
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