发明名称 |
Memory and refresh method for memory |
摘要 |
The present invention discloses a memory, and a refresh method for memory, which performs a normal access and refresh one after another within one operation cycle of SRAM. The memory of the present invention comprises a refresh enable which directs execution of refresh, a row address counter that addresses a row address of memory cells to be refreshed, and an execution circuit which refreshes the memory cells of the addressed row address in response to the direction of execution of refresh.
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申请公布号 |
US2002141271(A1) |
申请公布日期 |
2002.10.03 |
申请号 |
US20020063069 |
申请日期 |
2002.03.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SUNAGA TOSHIO;WATANABE SHINPEI |
分类号 |
G11C11/403;G11C11/406;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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