发明名称 |
Data slicer circuit |
摘要 |
The data slicer circuit has a first capacitor that holds a pedestal potential of the video signal; a second capacitor that calculates an average potential of signals existing in a period where a clock run-in signal of the multiplex signal is present and holds the average potential; and a comparator which compares the two held potentials. The comparator outputs a detection signal indicative of the presence of the multiplex signal when the potential held by the second capacitor is higher than that held by the first capacitor.
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申请公布号 |
US2002140856(A1) |
申请公布日期 |
2002.10.03 |
申请号 |
US20010918798 |
申请日期 |
2001.08.01 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
INOUE TETSUHIKO |
分类号 |
H04N7/025;H04N7/03;H04N7/035;H04N7/083;H04N7/087;H04N7/088;(IPC1-7):H04N7/00 |
主分类号 |
H04N7/025 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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