发明名称 |
DIGITAL-TO-ANALOG CONVERTER |
摘要 |
A decoder (21) selects one of FETs (F0 to F255) based on higher bits, and applies one of the voltages divided by a series circuit of resistors (r0 to r255) to an operational amplifier (40). Switches (30 to 33) of a current adder circuit (22) are switched by lower bits to turn on and off FETs (35 to 38). The currents flowing through the conducting FETs are combined, and the resulting current flows to a resistor (ra), across which a voltage appears. The operational amplifier (40) combines two input voltages to produce an output. A FET (24) and FETs (35 to 38) form a current mirror circuit, which prevents the voltage width of each LSB of higher and lower bits from changing if the current (i) through the series circuit of resistors (r0 to r255) changes because of irregularities of manufacturing processes.
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申请公布号 |
WO0141310(A9) |
申请公布日期 |
2002.10.03 |
申请号 |
WO2000JP08248 |
申请日期 |
2000.11.22 |
申请人 |
YAMAHA CORPORATION;NORO, MASAO;TODA, AKIHIKO |
发明人 |
NORO, MASAO;TODA, AKIHIKO |
分类号 |
H03M1/68;H03M1/06;H03M1/72;H03M1/74;H03M1/76;(IPC1-7):H03M1/68 |
主分类号 |
H03M1/68 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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