发明名称 |
A MULTIPLICATION LOGIC CIRCUIT |
摘要 |
A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters. |
申请公布号 |
WO02077792(A2) |
申请公布日期 |
2002.10.03 |
申请号 |
WO2002GB01343 |
申请日期 |
2002.03.21 |
申请人 |
AUTOMATIC PARALLEL DESIGNS LIMITED;TALWAR, SUNIL;RUMYNIN, DMITRIY |
发明人 |
TALWAR, SUNIL;RUMYNIN, DMITRIY |
分类号 |
G06F7/53;G06F7/52;G06F7/523;G06F17/50 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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