| 摘要 |
A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.
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