| 摘要 |
An electronic device that invalidates a memory write operation before a memory address predecode occurs. The electronic device uses several dynamic latches (16, 17, 25, 26) to assert complementary clock like memory address data to drive the associated predecode circuitry (8). A stack of serially connected transistors (18, 20, 22, 24 ...) is coupled to the input node of each dynamic latch to provide input node state control. By managing the operation of each stack of serially connected transistors, the dynamic latches may be prevented from asserting their complementary clock like memory address data to the associated predecode circuitry in order to invalidate a memory write operation.
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