| 摘要 |
An address generating circuit having: a first switch transistor, a second switch transistor, a fuse element, and a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of the first switch transistor and a second reset signal for controlling ON/OFF conditions of the second switch transistor. The address generating circuit also includes a latch circuit for latching and outputting a predetermined potential corresponding to a cut-off or a no cut-off condition of the fuse element. The first reset signal turns ON the first switch transistor during a first period immediately after the power supply is turned ON and always holds the first switch transistor in the OFF condition after the first period is completed. Furthermore, the second reset signal turns ON the second switch transistor at least during a second period after the first period and always holds the second switch transistor in the OFF condition after the second period is completed.
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