发明名称 System and method for automatically mapping state elements for equivalence verification
摘要 A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. "Don't care" input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.
申请公布号 US2002144215(A1) 申请公布日期 2002.10.03
申请号 US20010802616 申请日期 2001.03.09
申请人 HOSKOTE YATIN V.;DORESWAMY KIRAN B. 发明人 HOSKOTE YATIN V.;DORESWAMY KIRAN B.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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