发明名称 METHOD OF SHRINKING AN INTEGRATED CIRCUIT GATE
摘要 <p>An exemplary method of fabricating an integrated circuit includes patterning a first layer (28) having a first dimension where the first layer (28) is disposed over an etch stop layer (26) and a second layer (24); oxidizing the surface (30) of the patterned first layer (28); removing the oxidized surface (30) of the patterned first layer (28) resulting in a second dimension for the patterned first layer (28); and etching the etch stop layer (26) and the second layer (24) using the patterned first layer (28) having the second dimension as a hard mask.</p>
申请公布号 WO2002078071(A2) 申请公布日期 2002.10.03
申请号 US2001048596 申请日期 2001.12.12
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