Semiconductor memory device

摘要

A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block. <IMAGE>