Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell

摘要

An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds to the multiple bits in a memory cell. Latches (60-63, 65-67) are arranged in banks (A, B) and connected to the cells. The latches are controlled by control means (145, 146) so as to transfer data into the cells and to data terminals (25, 26). During writing and reading the data is transferred in parallel and serial modes.