| 摘要 |
A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and performing a resist flow operation on the semiconductor substrate after implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the resist flow operation on the semiconductor substrate includes baking the semiconductor substrate in an oven at about 100° C. to about 300° C. for about 5 minutes to about 30 minutes to thin down the resist mask and cause the edges of the resist mask to become rounded.
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