发明名称 Method of fabricating a MOS device with an ultra-shallow junction
摘要 A semiconductor substrate is provided with at least a gate formed on the semiconductor substrate. A first ion implantation process is performed to form a pocket implant region within the semiconductor substrate beneath the gate. Following the first ion implantation process, a first rapid thermal annealing (RTA) process is immediately performed to reduce TED effects resulting from the first ion implantation process. Thereafter, a second implantation process is performed to form a source extension doping region and a drain extension doping region within the semiconductor substrate adjacent to the gate. A source doping region and a drain doping region are then formed within the semiconductor substrate adjacent to the gate. Finally, a second RTA process is performed to simultaneously activate dopants in the source extension doping region, the drain extension doping region, the source doping region and the drain doping region.
申请公布号 US6458643(B1) 申请公布日期 2002.10.01
申请号 US20010681984 申请日期 2001.07.03
申请人 MACRONIX INTERNATIONAL CO. LTD. 发明人 LAI HAN-CHAO;LU TAO-CHENG;LIN HUNG-SUI
分类号 H01L21/265;H01L21/324;H01L21/336;H01L29/78;(IPC1-7):H01L21/823 主分类号 H01L21/265
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