| 摘要 |
The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. Interconnections are routed through vias extending through the thickness of the substrate. The vias are formed by etching holes through the silicon wafer, depositing an insulating layer on the sidewalls of the holes, depositing a barrier layer on the insulating layer, electrolytically depositing a metal selected from the group consisting of copper and nickel to form via plugs in the holes, and depositing another barrier layer over the via plugs. It is found that electrolytic deposition will successfully plug the holes even when the aspect ratio of the through holes is greater than four and the hole diameter less than 100 microns.
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