Delay locked loop circuit having duty cycle correction function and delay locking method

摘要

A delay locked loop circuit having a duty cycle correction function and a delay locking method are provided. The delay locked loop circuit includes a delaying portion for generating a first output signal by uniformly delaying an input first clock signal and generating a second output signal by variably delaying the first clock signal and an output signal generator for generating a second clock signal, the voltage level of which increases when the first output signal is transitioned from a first logic state to a second logic state and whose voltage level is reduced when the second output signal is transitioned from the second logic state to the first logic state. Accordingly, jitter that exists in the signal output from the delay locked loop circuit is reduced.