| 摘要 |
<p>The circuit includes an asynchronous reception unit (2) which receives input data by an asynchronous data transmission. The input data include an AT command with several characters which all include a start bit. A speed detection unit (3) detects the reception speed of the input data based on the start bit of a first character. A clock supply unit (5) generates a reception clock based on the reception speed and feeds the reception clock to the asynchronous reception unit. An input control unit (1) which activates a part of the input data as input data for the asynchronous reception unit based on the detected reception speed and supplies the activated input data part to the reception unit. The activated input data part starts from a start bit of a second character of the input data following the first character.</p> |
