STRUCTURE OF FLASH MEMORY DEVICE

摘要

PURPOSE: A structure of flash memory devices is provided to prevent a short between unit cells by preventing a poly bridge and a poly ribbon due to moat. CONSTITUTION: Memory cell array comprises a plurality of bit lines(52) and a plurality of word lines(53) arranged vertically to the bit lines. A first active region(42a) is formed at bottom of the bit lines(52) and parallel with the bit lines(52). A unit cell(B) is formed at the first active region(42a) of portions to cross the bit lines(52) and the word lines(53), and includes a gate stacked a floating gate(44) and a control gate. Adjacent two unit cells(B) are connected to the bit lines(52) via a bit line contact(50), and drain regions of the unit cells are isolated via an STI(Shallow Trench Isolation) field oxide(51a).