发明名称 BUS SYSTEM, BUS CONTROL SYSTEM AND BUS CONVERSION DEVICE
摘要 PROBLEM TO BE SOLVED: To minimize the lowering of responsiveness, bus availability and throughput caused by the competition of transactions, in a bus system where a plurality of modules are hierarchically connected through a bus. SOLUTION: A system bus 407 and I/O buses 411 to 413 are split buses and they support split transfer where the start cycle of reading access and a response data cycle can be split. When a processor 401 starts the reading of I/O 418 through a bus conversion device 410 and a system is not in the response data cycle of I/O 418, the system bus 407 and the I/O bus 413 are in usable states and therefore the transaction can be issued to I/O 419 from the processor 401 without being waited even if a processor 402 requests reading from I/O 419 of the same I/O bus 413.
申请公布号 JP2002278923(A) 申请公布日期 2002.09.27
申请号 JP20020017206 申请日期 2002.01.25
申请人 HITACHI LTD 发明人 KONDO NOBUKAZU;OKAZAWA KOICHI;SHINOZAKI MASATSUGU;OSAKA HIROSHI;HIRAMATSU MASATAKA;IWATSUKI KAZUKO
分类号 G06F13/36;H04L12/40;(IPC1-7):G06F13/36 主分类号 G06F13/36
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