发明名称 DATA LATCH DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a highly reliable data latch device capable of more surely excluding a malfunction caused by noises from an adjacently arranged circuit than in a conventional device. SOLUTION: Between a P channel transistor (23) of a data input tristate inverter (10) constructed on a semiconductor wafer by freely using thin film technology and one power source VDD, the circuit of P channel transistors (21 and 22) is interposed and between an N channel transistor (24) of the data input tristate inverter (10) and another power source (GND 27), the circuit of N channel transistors (25 and 26) is interposed. Then, the output of the circuit of N channel transistors (25 and 26) is turned on by ANDing a first write control signal (A) and a second write control signal (B), and the output of the circuit of P channel transistors (23 and 24) is turned on by ANDing an inverted signal (A<-> ) of the first write control signal and an inverted signal (B<-> ) of the second write control signal.
申请公布号 JP2002280879(A) 申请公布日期 2002.09.27
申请号 JP20010075155 申请日期 2001.03.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIYAZAKI YUMIKO;SHIMAMURA AKIMITSU
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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