METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, COMPUTER PROGRAM AND COMPUTER READABLE RECORDING MEDIUM

摘要

PROBLEM TO BE SOLVED: To design the layout of a clock signal easily while ensuring a desired performance even if the scale of a circuit being fabricated is enlarged at the time of hierarchic layout design including a clock signal across layers or blocks. SOLUTION: After ending placement of each block at step 110, clock signal connection information and information concerning to factors having an effect on the clock signal pattern is extracted for individual blocks at step 112. At steps 114-120, layout of the clock signal is designed based on these information and then layout of wiring in a block or between the blocks is designed. Since the volume of data being handled can be reduced effectively by extracting the information, fine design can be effected while adjusting delay of clock tree or skew.