| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer with which excellent communication quality can be realized by improving sprious characteristics in a lock state while securing high speed lock-up characteristics. SOLUTION: A switch circuit 10 inserted between a low-pass filter(LPF) circuit 103 and a voltage controlled oscillator(VCO) 104 is controlled by a control signal Scnt, and opening/closing of a feedback loop between the LPF circuit 103 and the VCO 104 is controlled. Namely, corresponding to the opening instruction of the feedback loop based on the control signal Scnt, the switch circuit 10 is opened, the feedback loop is opened and the operation of the feedback loop is stopped. Such stop operation is controlled by the control signal Scnt so the operation is performed during a period in which a pseudo correction pulse is outputted from a charge pump circuit 102 for each of phase comparing cycles of a phase comparator, and sprious caused by the pseudo correction pulse is suppressed. |
