| 摘要 |
PROBLEM TO BE SOLVED: To provide a fully digital PLL circuit with which stable output can be obtained. SOLUTION: An oscillating signal (fin ) 11 of a frequency higher than a desired frequency is outputted by an oscillator, a desired frequency (fin /L) is created by dividing the frequency by a frequency divider (1) 13, and the frequency is divided to a phase comparing frequency (fin /L/M) by a frequency divider (2) 12. A prescribed reference frequency (fref ) is divided to a frequency (fref /N) to compare the phase by a frequency divider (3) 14, the phase is compared with the frequency (fin /L/M) by an EXor circuit 15. Only in a block where 'H' is outputted, the pulse number of the oscillating signal (fin ) is counted by a pulse counter 16. This count value is held by a hold circuit 17 for each P clock for comparison generated from the reference frequency (fref ). Difference between the number of pulses saved at present and a number of pulses held next is obtained by a subtracting circuit 18, and the difference is reflected on the frequency (fin /L/M) divided by the frequency divider (2) 12 so that a signal of the desired frequency is obtained.
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