发明名称 |
METHOD FOR CALCULATING DELAY DISTRIBUTION, METHOD FOR EVALUATING CIRCUIT AND METHOD FOR EXTRACTING FALSE PATH |
摘要 |
PROBLEM TO BE SOLVED: To improve estimation accuracy by taking the correlation of performance between pieces of wiring or elements into consideration in calculation for a delay distribution of an integrated circuit. SOLUTION: Circuit information 11, performance distribution information 12 on wiring or elements in the integrated circuit, and the correlation information 13 of performance between the pieces of wiring or the elements are inputted (S11). A calculation point is selected (S12), and a delay distribution at the selected calculation point and the correlation of the delay distribution in a partial circuit including the calculation point are calculated on the basis of the performance distribution information 12 and the correlation information 13 (S13).
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申请公布号 |
JP2002279012(A) |
申请公布日期 |
2002.09.27 |
申请号 |
JP20010351885 |
申请日期 |
2001.11.16 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
TSUKIYAMA SHUJI;TANAKA MASAKAZU;FUKUI MASAHIRO |
分类号 |
G01R31/28;G01R31/317;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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