发明名称 Memory arrangement for computer has memory cell field, decoder circuit with word, bit line decoders, read output for reading from individual cells by selecting corresponding word, bit lines
摘要 The memory arrangement has a memory cell field (2) and a decoder circuit for reading from the memory cells (3) with a word line decoder (8), a bit line decoder (11) and a read output (14) for reading out the contents of each individual cell by selecting the word and bit lines corresponding to individual cells. Independent claims are also included for the following: a method of reading from a memory arrangement and a computer arrangement with a processor and memory arrangement.
申请公布号 DE10111454(A1) 申请公布日期 2002.09.26
申请号 DE20011011454 申请日期 2001.03.09
申请人 INFINEON TECHNOLOGIES AG 发明人 ROESNER, WOLFGANG;LUYKEN, R. JOHANNES;HOFMANN, FRANZ;KRETZ, JOHANNES
分类号 G11C8/10;G11C13/02;H01L27/108;(IPC1-7):G11C8/10;G11C7/00 主分类号 G11C8/10
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