| 摘要 |
The invention relates to methods and apparatus that selectively multiply an analog signal by zero (0), one (1), and negative one (-1) at high speeds. In one embodiment, the analog signal corresponds to an integration result of a transition from a first data bit to a second data bit in a serial data bitstream. Advantageously, the multiplier circuit is well adapted to relatively high-frequency operation by providing a balanced load to a driver circuit such that the selected multipliers of the multiplier circuit can switch in a substantially symmetrical manner. In one embodiment, the driver circuit includes a data transition identifier circuit.
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