Signal delay circuit has demultiplexer, signal delay lines of different lengths connected to output; connected signal is delayed by defined period proportional to signal delay line length

摘要

The circuit has at least one controllable demultiplexer (22) with an input (21) for the signal to be delayed and several outputs (23); the input is connected to one of the outputs depending on a control signal. Several signal delay lines (27) with different lengths are connected to an output and the connected signal is delayed by a defined period proportional to the line length of the signal delay line.