System and method for high speed integrated circuit device testing utilizing a lower speed test environment

摘要

A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2X frequency clock from the 1X frequency external clock signals (two 1X clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.