发明名称 |
Clock controller for AC self-test timing analysis of logic system |
摘要 |
A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.
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申请公布号 |
US2002138157(A1) |
申请公布日期 |
2002.09.26 |
申请号 |
US20010812321 |
申请日期 |
2001.03.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LO TINCHEE;FLANAGAN JOHN D. |
分类号 |
G01R31/3185;(IPC1-7):G05B11/01 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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