发明名称 |
Circuit for biasing a bulk terminal of a MOS transistor |
摘要 |
A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.
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申请公布号 |
US6456150(B1) |
申请公布日期 |
2002.09.24 |
申请号 |
US20000661601 |
申请日期 |
2000.09.14 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
SACCO ANDREA;MICHELONI RINO;SCOTTI MARCO |
分类号 |
H03K19/003;(IPC1-7):H03K3/01 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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