| 摘要 |
The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the present invention, in which the first conductive gate layer is etched to form a steep-gate structure or a taper-gate structure. The metal layer is encapsulated by a second masking dielectric layer formed on the top and a first dielectric spacer formed on both sides, no interaction would occur between the metal layer and the first conductive gate layer, a highly-conductive nature of the metal layer for gate interconnection can be preserved. A thick silicide layer is formed by a two-step self-aligned silicidation process and a conductive barrier-metal layer is formed to eliminate the interaction between the thick silicide layer and the first conductive gate layer, a highly conductive nature of the thick silicide layer for gate interconnection can be obtained. Moreover, the field-emission between the gate and the shallow moderately doped source/drain diffusion region can be minimized by a graded gate-oxide layer formed near the gate edges and the field emission between the trench corners of the semiconductor substrate and the gate can be completely eliminated by a flat shallow-trench-isolation structure.
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