发明名称 |
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) |
摘要 |
A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
|
申请公布号 |
US6455377(B1) |
申请公布日期 |
2002.09.24 |
申请号 |
US20010765040 |
申请日期 |
2001.01.19 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
ZHENG JIA ZHEN;CHAN LAP;QUEK ELGIN;SUNDARESAN RAVI;PAN YANG;LEE JAMES YONG MENG;LEUNG YING KEUNG;PRADEEP YELEHANKA RAMACHANDRAMURTHY |
分类号 |
H01L21/336;H01L21/337;H01L29/10;H01L29/78;H01L29/80;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|