| 摘要 |
A duty cycle discriminating circuit used, for example, in a VTR includes an up/down counter with sign bit for counting up or counting down a count clock signal depending on a potential level of a signal to be discriminated. It also includes an up counter for counting up the count clock signal, and an addend data generating circuit for producing an addend data having a value corresponding to a predetermined proportion of a count value of the up counter. There is an addition circuit with sign bit for adding a count value of the up/down counter and the addend data produced by the addend data generating circuit. The sign bit of the addition circuit is outputted as a discrimination result signal of the duty cycle discriminating circuit. The predetermined proportion of the count value up counter is specified to perform duty cycle discrimination of the signal by using a desired threshold point.
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