发明名称 DATA SLICING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a data slicing circuit that generates an optimum data slice level with respect to VBI(vertical blanking interval) signals having different different standards to separate data. SOLUTION: The data slice circuit is provided with a line detection circuit 33, that outputs a line detection pulse PLC only in the case of detecting a line with a VBI signal having a CRI(clock-run-in) signal superimposed thereon, and outputs a line detection pulse PLR only for a period, when detecting a line with a VBI signal having a reference signal superimposed thereon, a window pulse generating circuit 34 that outputs pulses PCRI, PPED to change a period averaging the VBI signal in response to the pulses PLC, PLR, a data slice reference voltage detection circuit 35 that samples and holds the average voltage of the VBI signal clamped for a period of output pulses PCR, PPED only, and a data slicing level generating circuit 37, that adds a DC voltage changed in response to the detected pulses PLC, PLR to an output voltage of the circuit 35.
申请公布号 JP2002271648(A) 申请公布日期 2002.09.20
申请号 JP20010069215 申请日期 2001.03.12
申请人 SONY CORP 发明人 ORII TOSHIHIKO
分类号 H04N5/08;H04N7/035;H04N7/083;H04N7/087;H04N7/088;(IPC1-7):H04N5/08 主分类号 H04N5/08
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