| 摘要 |
generation of fully known signal. SUBSTANCE: device has clock generator, address decoder, memory unit from whose output generated signal is picked off, and mode-of-operation control unit with trigger, mode-control, and electronic-switch control signals. Signal generated in digital form is pre-entered in device memory unit. Address decoder has circuit for generating signal indicating end of memory location address search. Signal taken off memory unit output changes device over to ready mode for data read/write out/in memory unit. Address decoder also has electronic switch controlled for changing address decoder input over to clock sequence reception from inherent or peripheral generators. Signal arriving from control unit acts on switch so that in generation mode address decoder input is connected to inherent generator and in memory-unit write mode, to peripheral one. EFFECT: enhanced operating reliability and memory capacity, enlarged functional capabilities of device. 7 dwg
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