PERIPHERAL COMPONENT INTERCONNECT BUS MEMORY ADDRESS DECODING

摘要

A peripheral component interconnect (PCI) bus memory addressing system comprising a memory address decoder and disconnection means connected to a P CI bus, the disconnection means being arranged to disconnect one or more signal s of the PCI bus from a first PCI device, wherein the memory address decoder is arranged to selectively activate the disconnection means such that an address which fall s within an address range identified in a base address register of the first PCI device and a base address register of a second PCI device will be received by the second PCI device but not by the first PCI device.