发明名称 DECODER
摘要 PROBLEM TO BE SOLVED: To provide a decoder for convolution codes, capable of reducing trouble of calculation and the number of selection processing or decreasing the required capacity of a memory, while keeping an proper characteristic (error rate), and to provide a digital receiver using the same. SOLUTION: In a decoder of a digital receiver, a bit metric calculation section 100 is provided with differential bit metric calculation sections 101-106, a parallel-serial conversion section 110 and a level conversion section 120. The sections 101-106 input a real part Re yi } or an imaginary part Im yi } of a receiving signal point which is to be inputted respectively and output differential bit metrics dm b0 } to dm b5 }. The differential bit metrics are inputted into the section 110 and are outputted in a prescribed order, which has been separately predetermined. The outputted data are inputted into the section 120 and are outputted to the later stage after bit precision and the data range of a soft decision value is restricted.
申请公布号 JP2002271211(A) 申请公布日期 2002.09.20
申请号 JP20010069038 申请日期 2001.03.12
申请人 HITACHI LTD 发明人 OKUBO TAKASHI;NOGAMI HIROSHI
分类号 G06F11/10;H03M13/41;H04J11/00;H04L1/00;H04L27/34 主分类号 G06F11/10
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