发明名称 COUNTER POTENTIAL GENERATING CIRCUIT, PLANAR DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce power consumption for preparing a counter potential to be supplied to a counter electrode at the time of a standby state performing the display of a still picture in a counter potential generating circuit for supplying the counter potential to a planar display device. SOLUTION: In a first display period (normal display state), a power source voltage VDD is supplied to a voltage dividing circuit 6 by turning switches SW1, SW2 ON with a switch control circuit 7 and a counter potential is made to be generated by inputting the setting voltage of the counter potential which is divided in this voltage dividing circuit 6 to an output amplifier circuit 1 and in a second display period (still picture display state), a current is made so as not to be supplied from the power source voltage VDD to the circuit 6 by turning the switches SW1, SW2 OFF with the circuit 7 and a counter potential is made to be generated by inputting the setting voltage of the counter potential stored in a capacitor C to the output amplifier circuit 1.
申请公布号 JP2002268611(A) 申请公布日期 2002.09.20
申请号 JP20010069200 申请日期 2001.03.12
申请人 TOSHIBA CORP;TOSHIBA ELECTRONIC ENGINEERING CORP 发明人 WARASHINA RIKIYA
分类号 G02F1/133;G09G3/20;G09G3/36;(IPC1-7):G09G3/36 主分类号 G02F1/133
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