| 摘要 |
electrical engineering. SUBSTANCE: circuit to generate negative voltage has first transistor Tx2 which first lead is connected to input lead E and which second lead is connected to output lead A of circuit and gate lead of it is connected via first capacitor Cb2 to first lead of clock signal, to second transistor Ty2 which first lead is connected to gate lead of transistor Tx2, which second lead is connected to second lead of transistor Tx2 and which gate lead is connected to first lead of transistor Tx2 and to second capacitor Cp2. First lead of capacitor Cp2 is connected to second lead of transistor Tx2 and second lead of capacitor is connected to second lead of clock signal. Transistors Tx2 and Ty2 are MOS transistors built in accord with technology of triple pocket. First lead of third transistor Tz2 is connected to second lead of transistor Tx2, second lead of transistor Tz2 is connected to pocket/pockets Kw carrying transistors Tx2, Ty2, Tz2 and gate lead of transistor Tz2 is connected to first lead of transistor Tx2. EFFECT: enhanced efficiency thanks to reduction of leakage currents. 6 cl, 6 dwg
|
