发明名称 METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To miniaturize an MOS field effect transistor, without deteriorating the breakdown voltage of it. SOLUTION: The electric field relieving layer of gate overlapping structure is arranged by bringing it into contact with a drain region, a distance between the electric field relieving layer and a high concentration layer is spread and an electric field is relieved. Since an equal potential line is bent by a gate insulating film, the electric field is relieved much more. A punch-through stopper layer of a gate overlap structure is arranged by bringing it into contact with the source region, the spreading of a depletion layer to the source region is suppressed, and gate length made fine.
申请公布号 JP2002270825(A) 申请公布日期 2002.09.20
申请号 JP20010064318 申请日期 2001.03.08
申请人 HITACHI LTD 发明人 OYANAGI TAKASUMI;WATANABE TOKUO
分类号 H01L21/336;H01L21/8234;H01L21/8238;H01L27/088;H01L27/092;H01L29/08;H01L29/10;H01L29/78;(IPC1-7):H01L29/78;H01L21/823 主分类号 H01L21/336
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