CHARGE PUMP PHASE LOCKED LOOP CIRCUIT

摘要

A P-stage shift register or counter (156) is added to the charge pump (128) and/or to the phase frequency detector (126) of a phase locked loop circuit (150) to keep the output clock stable enough from the locked frequency value and available for long enough after the input reference clock has been removed. This mode is called the phase locked loop (PLL) free running mode (FRM) and is activated as soon as the device has detected the loss of the input reference clock of the phase locked loop. Once the free running mode is activated the charge pump (128) automatically enters its high impedance state resulting in a slower frequency shift process at the PLL output in comparison to a conventional PLL. This main advantage of this PLL circuit is that the system clock is kept running for long enough so that the system can issue a fualt report through another logic and memory device when the reference clock is suddenly removed either accidentally or not.