发明名称 |
Technique to mitigate short channel effects with vertical gate transistor with different gate materials |
摘要 |
This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.
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申请公布号 |
US2002130378(A1) |
申请公布日期 |
2002.09.19 |
申请号 |
US20010808114 |
申请日期 |
2001.03.15 |
申请人 |
FORBES LEONARD;TRAN LUAN C.;AHN KIE Y. |
发明人 |
FORBES LEONARD;TRAN LUAN C.;AHN KIE Y. |
分类号 |
H01L21/28;H01L21/8242;H01L29/49;H01L29/78;(IPC1-7):H01L29/76;H01L29/94;H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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