发明名称 |
Digital data processing system |
摘要 |
A digital data processing system minimizes overall power consumption in a system having embedding large capacity RAMs. Power consumption is reduced by establishing sufficient set-up times when driving plural RAM blocks that have been held in a standby state. A RAM access controller is interposed between an oscillator and the RAM blocks, and controls a master clock generated from the oscillator to secure setup times of the RAM blocks.
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申请公布号 |
US2002133677(A1) |
申请公布日期 |
2002.09.19 |
申请号 |
US20010002583 |
申请日期 |
2001.11.01 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI KWANG-JU |
分类号 |
G06F12/00;G06F13/42;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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