发明名称 Semiconductor device having reduced interconnect-line parasitic capacitance
摘要 A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.
申请公布号 US2002132466(A1) 申请公布日期 2002.09.19
申请号 US20010940852 申请日期 2001.08.29
申请人 LIN BEN MIN-JER;WANG SHENG-JEN 发明人 LIN BEN MIN-JER;WANG SHENG-JEN
分类号 H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/476 主分类号 H01L21/768
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