发明名称 High performance equalizer with enhanced DFE having reduced complexity
摘要 An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.
申请公布号 US2002131490(A1) 申请公布日期 2002.09.19
申请号 US20010946648 申请日期 2001.09.04
申请人 ALLPRESS STEVE A.;LI QUINN 发明人 ALLPRESS STEVE A.;LI QUINN
分类号 H04L25/03;(IPC1-7):H03K5/159 主分类号 H04L25/03
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