发明名称 |
6F2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6F2 dram array and a method of isolating a single row of memory cells in a 6F2 dram array |
摘要 |
The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.
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申请公布号 |
US2002130348(A1) |
申请公布日期 |
2002.09.19 |
申请号 |
US20010810933 |
申请日期 |
2001.03.16 |
申请人 |
TRAN LUAN C. |
发明人 |
TRAN LUAN C. |
分类号 |
H01L21/8242;H01L27/02;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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