Personalisierte Fläche eines Leiterrahmes geformt oder halb-geätzt zur Reduzierung mechanischer Beanspruchung an den Chipkanten
摘要
A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.
申请公布号
DE69527761(D1)
申请公布日期
2002.09.19
申请号
DE1995627761
申请日期
1995.11.02
申请人
SIEMENS AG;INTERNATIONAL BUSINESS MACHINES CORP., ARMONK
发明人
CONRU, HAROLD WARD;FROEBEL, FRANCIS EUGENE;GREGORITSCH, JR.;RIELEY, SHELDON COLE;STARR, STEPHEN GEORGE;UTTRECHT, RONALD ROBERT;WHITE, ERIC JEFFREY;POHL, JENS GUENTER