Method for testing for the presence of faults in digital circuits

摘要

A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN-1 and then simulating the vector set TN-1 against the fault list FN. Any vector from the set TN-1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set Tt. Embodiments of the invention are described.