| 摘要 |
The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of a semiconductor wafer. The method of the present invention involves the deposition of a first dielectric layer and an undoped polysilicon layer, respectively, in the periphery circuit region of the silicon substrate of the semiconductor wafer. Thereafter, a plurality of gates and lightly doped drains of the MOS transistors are formed in the memory array area of the semiconductor wafer, with each gate comprising a second dielectric layer, a doped polysilicon layer, a silicide layer and a protection layer, respectively. Next, both the undoped polysilicon layer and the first dielectric layer in the periphery circuit region are etched to form gates of each MOS transistor in the periphery circuit region. Finally, lightly doped drains, spacers, sources and drains of each MOS transistor in the periphery circuit region are formed. The implantation processes that form the sources and drains also simultaneously implant the undoped polysilicon layers of each gate.
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